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aic157 3 5- b it d ac , synchronous p wm power regulator w ith simple p wm power regulator, ldo and linear controller analog integrations corporation 4f, 9, industry e. 9th rd, science based industrial park, hsinchu taiwan, roc www.analog.com.tw ds-1 573- 01 sep 10, 01 tel: 886-3-5772500 fax: 886-3-5772510 1 n features l compatible with hip60 20 . l provides 4 regulated voltages for microprocessor core, agp bus, memory and gtl bus power. l ttl compatible 5-bit digital-to-analog core output voltage selection. range from 1.3v to 3.5v. 0.1v steps from 2.1v to 3.5v. 0.05v steps from 1.3v to 2.05v. l 1.0% pwm output voltage for vcore . l 3% pwm output voltage for agp bus. l 3 .0% reference voltage for chipset and/or c a - che mem o ry and vgtl. l simple voltage-mode pwm control with b uilt in i nternal compensation network s . l n-channel mosfet driver for pwm buck co n - verters . l linear controller drives compatible with both n ? chanel mosfet and npn bipolar series pass transistor. l operates from +3.3v, +5v and +12v i n puts. l fast transient response. l full 0% to 100% duty ratios. l adjustable current limit without external sense r e sistor. l microprocessor core voltage protection against upper mosfet shorted to +5v . l power good output voltage monitor. l over-voltage and over-current fault monitors. l 200khz free-running oscillator programmable up to 70 0khz. n applications l full motherboard power regulation for compu t ers. n description the aic157 3 combines two pwm voltage mode controllers and two linear controller s as well as the monitoring and protection functions in this chip. one pwm controller regulates the microprocessor core voltage with a synchronous rectified buck converter. the second pwm controller provides agp bus 1.5v or 3.3v power with a standard buck converter. t wo linear controllers regulate power for the 1.5v gtl bus and 1.8v power for the chip set core voltage and/or cache memory circuits. an integrated 5 bit d/a converter that adjusts the microprocessor core voltage from 2.1v to 3.5v in 0.1v increments and from 1.3v to 2.05v in 0.05v increments. the second pwm controller for agp bus power is selectable by means of select pin status for 1.5v or 3.3v with 3% accuracy. two linear controller s drive with external n-channel mosfet s to provide 1.5v 3 % and fixed output voltage 1.8v 3% . this chip monitors all the output voltages. power good signal is issued when the core voltage is within 10% of the dac setting and the other levels are above their under-voltage levels. over-voltage protection for the core output uses the lo w er n- channel mosfet to prevent output voltage above 116% of the dac se t ting. the pwm over-current function monitors the output current by using the voltage drop across the upper mosfet?s r ds( on ) , eliminating the need for a cu r - rent sensing resistor .
aic157 3 2 n application circuit + + + + + + ugate1 ugate2 phase1 phase2 lgate1 pgnd vsen2 fb1 select nc vaux vsen1 drive3 vid0 vsen3 vid1 vid2 vid3 vid4 pgood drive4 fault/rt vesn4 ss 7 m h 3 m h 4.7 m f 8 13 7 6 5 4 3 1nf 1nf c7 c5 1000 m f*3 1000 m f*7 20 0.22 m f c6 680k 10k r2 r1 10v 680 m f*7 c in r3 l1 v out1 21 l3 22 c out1 ocset1 23 24 25 26 27 gnd +5v in 1 m h q2 q1 9 3.3v or 1.5v v out2 q5 q4 q3 c out3 c out4 c out2 14 css gnd 1.8v v out4 15 11 16 v out3 19 18 1.5v +3.3v in 28 1 +12v in ocset2 l2 10 2 vcc 17 12
aic157 3 3 n ordering information order number pin configuration aic157 3 - c x aic157 3 cs (so2 8 ) packaging type s: small outline 1 3 4 2 5 7 6 8 9 10 vid 1 phase2 vid 4 vid 3 ugate2 vid 2 vsen2 vid0 ocset2 pgood 11 12 ss select phase1 vcc ugate1 ocset1 lgate1 pgnd 20 1 9 vsen1 vsen 3 fb 1 nc 28 26 27 25 24 23 21 22 1 8 1 7 gnd drive3 13 1 4 vsen4 fault/rt 1 6 15 drive4 vaux n absolute maximum ratings supply voltage, vcc ...............?????.....???? . ........?.. ??..................... +15v pgood, fault and gate voltage .....??? .. ...??? .. ?.... gnd -0.3v to v cc +0.3v input, output , or i/o voltage ......?...?????????. . ??............ gnd -0.3v to 7v recommended operating conditions supply voltage ; vcc ??..????........... ?................... +12v10% ambient t emperature range ??..?? .. ???................. 0 c~70 c junction temperature range ??....? . ??? . ................. 0 c~1 25 c thermal information thermal resistance, q ja soic package ????????????? .. ? .. ? . ............. 7 0 c/w soic package (with 3in 2 of copper) ?...? .. ?? .. .....?......... 5 0 c/w maximum junction temperature (plastic package) ??????? .. ??...... 150 c maximum storage temperature range ???????? .. ???.... -65 c ~ 150 c maximum lead temperature (soldering 10 sec) ??????????.. ?... 300 c
aic157 3 4 n electrical characteristics (vcc=12v, t a =25 c , unless otherwise spec i fied) parameter test conditions symbol min. typ. max. unit vcc supply current supply current ugate1, lgate1, ugate2, drive3 and drive4 open i cc 3 ma power on reset rising vcc threshold vocset=4.5v v ccthr 10.4 v falling vcc threshold vocset=4.5v v ccthf 8.2 v rising vaux threshold vaux thr 2.5 v vaux threshold hy s teresis vaux hys 500 mv rising vocset1 threshold v ocseth 1.26 v oscillator free running frequency rt=open f 17 0 200 2 30 khz total variation 6k w 2.0v 3.3 v pwm2 reference voltage tolerance 3 % 1.5v and 1.8v linear regulators ( out3, out4) regulation 3 % vsen3 regulation vol t age v reg3 1.5 v vsen4 regulation vol t age v reg4 1.8 v under-voltage level ( v sen /v reg ) v sen rising v senuv 75 % under-voltage hysteresis (v sen /v reg ) v sen falling 5 % output drive current ( all linears ) v aux -v drive > 0.6v 20 30 ma
aic157 3 5 n electrical characteristics ( continued ) parameter test conditions symbol min. typ. max. unit synchronous pwm controller amplifier dc gain (g.b.d.) 80 db gain-bandwidth product (g.b.d.) g bwp 13 mhz slew rate (g.b.d.) note 1. s r 6 v/ m s pwm controller gate drivers u gate1,2 upper drive source v cc =12v, v u gate = 6v i ugh 0.9 a u gate1,2 upper drive sink v u gate =1v r ugl 2.8 3.5 w lower drive source v cc =12v, v lgate =1v i lgh 1 a lower drive sink v lgate =1v r lgl 2.2 3.0 w protection vsen1 over-voltage ( v sen1 /dacout) v sen1 rising ovp 116 120 % fault sourcing current v cc - v fault /r t =2.0v i ovp 20 ma ocset1,2 current source v ocset =4.5vdc i ocset 170 200 230 m a soft-start current i ss 25 m a power good v sen1 upper threshold ( v sen1 /dacout ) v sen1 rising 108 111 % v sen1 under-voltage ( vsen1/dacout ) v sen1 falling 92 95 % v sen1 hysteresis (vsen1/dacout) upper and lower threshold 2 % p good voltage low i pgood =-4ma v pgood 0.4 0.8 v note 1. without internal compensation network, the gain bandwidth product is 13mhz. being associated with internal compensation networks, the bode plot is shown in fig. 3, ? internal compensation gain of pwm error ampl i fier ? .
aic157 3 6 n typical performance characteristics fig. 1 soft start interval with 4 outputs and p good pgood ss v out3 v out2 v out1 v out4 ss vdac=3.5v vdac=2v vdac=1.3v fig. 2 soft start initiates pwm output 1k 10k 100k 1m -5 0 5 10 15 20 25 30 90 c gain (db) frequency (hz) fig 3. internal compensation gain of pwm error amplifier -40 c 22 c 10k 100k 1m 1k 10k 100k 1m 10m r t pull up to 12v resistance ( w ) switching frequency (hz) r t pull down to gnd fig. 4 r t resistance vs. frequency switching frequency (hz) 200k 30 0 k 400k 500k 600k 700k 8 0 0k 900k 1m 0 20 40 60 80 100 120 140 160 i cc ( ma) vcc=12v c ug1 =c lg1 =c ug2 =c c=4.7nf c=3.3nf c=1.5nf c=650pf c=0 fig. 5 supply current vs. frequency ss inductor current 5a/div over load applied fault fig. 6 over current on inductor
aic157 3 7 n typical performance characteristics (continued) fig. 7 load transient of linear controller -40 -20 0 20 40 60 80 100 120 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 f sw =200khz fig. 8 temperature vs. switching frequency drift switching frequency drift (%) temperature ( c) -40 -20 0 20 40 60 80 100 120 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 ocset current = 200 m a fig. 9 temperature vs. ocset current drift ocset current drift (%) temperature ( c) -40 -20 0 20 40 60 80 100 120 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 - 0 . 1 0.0 0.1 0.2 0.3 0.4 fig. 10 temperature drift of 9 different parts vreg2=3.3v vsen2 voltage drift (%) temperature ( c) - 40 - 20 0 20 40 60 80 100 120 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0 . 1 0.0 0.1 0 . 2 0 .3 0.4 fig. 11 temperature drift of 13 different parts dacout=1. 6 v pwm output voltage drift (%) temperature ( c) -40 -20 0 20 40 60 80 100 120 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 fig. 12 temperature drift of 9 different parts vreg4=1.8v vsen4 voltage drift (%) temperature ( c)
aic157 3 8 n typical performance characteristics (continued) v out1 0 to 20a load step fig. 13 load transient of pwm output 0 to 20a load step v out1 fig. 14 stringent load transient of pwm output fig. 15 fb voltage accuracy number of parts accuracy (%) -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0 10 20 30 40 50 60 70 ta=25 c dacout=1.6v 3 std.=0.56% mean= -0.006% fig. 16 vsen3 voltage accuracy number of parts -1.0 -0.5 0.0 0.5 1.0 0 10 20 30 40 50 60 70 80 ta = 25 c mean = 0.16% 3 std.=1% accuracy (%)
aic157 3 9 n block diagram off ramp2 ramp1 dacout inhb ov vsen1 por ss reset oc1 oc1 up luv ss ramp2 por rt fault / inhb inhb vaux gate control vcc 4.5v 25ua vcc 3 p, 2 z comp. nc comp1 fb1 vcc vcc drv-h pgnd control gate drv-l r r r 0.2v 4v 1.5v or 3.3v vaux vaux select drive4 drive3 logic soft start vsen4 vsen3 ocset2 ocset1 vcc phase2 ugate2 vsen2 phase1 ugate1 lgate1 gnd ss vid4 vid3 vid2 vid1 vid0 x 75% comp2 drv2 amp2 error converter ttl d/a x 115% latch current 200ua 200ua x 75% oscillator amp1 error reset power on x 110% x 90% vsen1 pgood vcc (3) counter latch fault over
aic157 3 10 n pin descriptions pin 1: ugate 2 : external high-side n-mosfet gate drive pin. connect ugate 2 to gate of the external high-side n- mosfet . pin 2: phase2: over-current detection pin. co n - nect the phase2 pin to source of the external high-side n- mosfet. this pin detects the voltage drop across the high-side n-mosfet r ds( on) for over- current prote c tion. pin 7: vid4: pin 6: vid3: pin 5: vid2: pin 4: vid1: pin 3: vid0: 5bit dac voltage select pin. ttl- compatible inputs used to set the internal voltage reference vdac. when left open, these pins are internally pulled up to 5v and provide logic ones. the level of vdac sets the converter output voltage as well as the pgood and ovp thres h olds. table 1 specifies the vdac vol t - age for the 32 combinations of dac inputs. pin 8: pgood: power good indicator pin. pgood is an open drain output. this pin is pulled low when the converter output is 10% out of the vdac reference voltage or the other outputs are below their under-voltage thresholds. the pgood output is open for vid codes that inhibit operation. see t a ble 1. pin 9: ocset2: current limit sense pin. connect a resistor r ocset from this pin to the drain of the external high-side n-mosfet. r ocset , an internal 200 m a current source (iocset), and the upper n-mosfet on - resistance (r ds(on) ) set the over- current trip point according to the following equation: ds(on) ocset ocset peak r r i i = pin 10: vsen2: connect this pin to the output of the standard buck pwm regul a - tor. the voltage at this pin is regulated to the 1.5v/3.3v pred e - termined by the logic low/high level st a tus of the select pin. this pin is also monitored by the pgood co m parator circuit. pin 11: select: this pin determines the output voltage of the agp bus switching regulator. a low ttl input sets the output voltage to 1.5v, while a high input sets the output vol t - age to 3.3v. pin 12: ss: soft-start pin. connect a c apac i - tor from this pin to ground. this capacitor, along with an internal 25 m a (typically) current source, sets the soft-start interval of the converter. pulling this pin low will shut down the ic. pin 13: fault/rt: frequency adjustment pin. connecting a resistor (rt) from this pin to gnd, increasing the frequency. connecting a resistor (rt) from this pin to vcc, d e -
aic157 3 11 creasing the frequency by the following figure (fig.3). this pin is 1.26v during normal operation, but it is pulled to vcc in the event of an over-voltage or over-current co n dition. ? ? ? ? ? + = t r k . f f 2 25 1 0 , r t pulled to gnd ? ? ? ? ? - - = t r v vcc f f 5 26 . 1 1 0 , r t pulled to vcc, where 0 f is free run fr e quency. pin14: vsen4: connect this pin to the 1.8v linear regulator?s output. this pin is monitored for under-voltage events. pin15: drive4: connect this pin to the gate of the external n-mos to supply 1.8v power for memorey r e - quirement. pin 16: vaux: the +3.3v input voltage at this pin is monitored for power-on ? reset (por) purpose. connect to +5v provides boost current for the linear regulator?s output. pin 17: gnd: signal gnd for ic. all voltage levels are measured with respect to this pin. pin 18: drive3: connect this pin to the gate of the external n-mos for providing 1.5v power to gtl bus. pin 19: vsen3: connect this pin to the 1.5v linear regulator?s output. this pin is monitored for under-voltage events. pin 20: comp1: external compensation pin of the synchronous pwm converter. this pin is connected to error amplifier output and pwm co m - parator. a rc network is co n - nected to fb1 in to compensate the voltage control feedback loop of the co n verter. pin 21: fb1: the error amplifier inverting i nput pin of the synchronous pwm converter. the fb1 pin and comp1 pin are used to compe n - sate the voltage-control feedback loop. pin 22: vsen1: synchronous pwm converter?s output voltage sense pin. co n - nect this pin to the converter ou t - put. the pgood and ovp co m - parator circuits use this signal to report output voltage status and for over-voltage protection fun c - tion. pin 23: ocset1: current limit sense pin. connect a resistor r ocset from this pin to the drain of the external high-side n-mosfet. r ocset , an internal 200 m a current source (i ocset ), and the upper n-mosfet on- resistance ( r ds( on) ) set the over- current trip point according to the following equ a tion: ds(on) ocset ocset peak r r i i = the voltage at this pin is also moni tored for power-on reset (por) purpose. pin 24: pgnd: driver power gnd pin. pgnd should be connected to a low i m - pedance ground plane in close to lower n-mosfet source. pin 25: lgate1: lower n-mosfet gate drive pin of the synchronous pwm co n - verter. pin 26: phase1: over-current detection pin. co n -
aic157 3 12 nect the phase1 pin to source of the external high-side n- mosfet. this pin detects the voltage drop across the high-side n-mosfet r ds( on) for over- current prote c tion. pin 27: ugate1 :external high-side n-mosfet gate drive pin. connect ugate1 to the synchronous pwm co n - verter?s gate of the external high- side n- mosfet . pin 28: vcc: the chip power supply pin. it a lso provides the gate bias charge for all the mosfets controlled by the ic. recommended supply voltage is 12v. the voltage at this pin is monitored for power-on- reset purpose. n applications information the AIC1573 is designed for microprocessor co m - puter applications with 3.3v and 5v power, and 12v bias input. this ic has two pwm controller and two linear controllers. the first pwm (pwm1) controller is designed to regulate the microproce s - sor core voltage (vout1) by driving 2 mosfets (q1 and q2) in a synchronous rectified buck co n - verter configuration. the core voltage is regulated to a level programmed by the 5 bit d/a converter. the second pwm (pwm2) controller is designed to regulate the advanced graphics port (agp) bus voltage (vout2). pwm2 one of the linear contro l - lers is designed to regulate the advanced graphic port (agp) bus voltage (vout2). pwm2 controller drives a mosfet (q3) in a standard buck converter and regulates the output voltage to a digitally- programmable level of 1.5v or 3.3v .selection of either output voltage is achieved by applying the proper logic level at the select pin. the two linear controllers supply the 1.5v gtl bus power (vout3) and 1.8v memory power (vout4). the power-on-reset (por) function continually monitors the input supply voltage +12v at vcc pin, the 5v input voltage at ocset pin, and the 3.3v input at vaux pin. the por function init i ates soft- start operation after all three input supply voltage exceeds their por thres h olds. soft-start the por function initiates the soft-start sequence. a n internal 2 5 a current source charges an exte r - nal capacitor (c ss ) on the ss pin to 4.5v. the pwm error amplifier reference input (non-inverting terminal) and output (comp1 pin) is clamped to a level proportional to the ss pin voltage. as the ss pin voltage slew from 1v to 4v, the output clamp generates phase pulses of increasing width that charge the output capacitors. after the output vol t - age increases to approximately 70% of the set value, the reference-input clamp slows the output voltage rate-of-rise and provides a smooth transition to the final set voltage. additionally, all linear reg u - lator?s reference inputs are clamped to a voltage proportional to the ss pin voltage. this method provides a rapid and controlled output vol t age rise. fig.1 and fig. 2 show the soft-start sequence for the typical application. the internal oscillator?s triang u - lar waveform is compared to the clamped error a m - plifier output voltage. as the ss pin voltage i n - creases, the pulse width on phase pin increases. the interval of increasing pulse width continues u n - til output reaches sufficient voltage to transfer co n - trol to the input refe r ence clamp.
aic157 3 13 each linear output initially follows a ramp. when each output reaches sufficient voltage the input re f - erence clamp slows the rate of output voltage rise. the pgood signal toggles ?high? when all output voltage levels have exceeded their under-voltage levels. fault protection all four outputs are monitored and protected against extreme overload. a sustained overload on any output or over-voltage on pwm1 output di s - ables all outputs and drive the fault/rt pin to vcc. + + 0.15v ov over current latch 4.0v ss oc1 r luv q s fault vcc fault latch por q r s r s counter inhibit oc2 fig. 1 7 simplified schematic of fault logic a simplified schematic is shown in figure 1 7 . an over-voltage detected on vsen1 immediately sets the fault latch. a sequence of three over-current fault signals also sets the fault latch. the over- current latch is set dependent on the status of the over-current (oc1 and oc2), linear under-voltage (luv) and the soft-start signal. an under-voltage event on either linear output (vsen3, vsen4) is ignored until the soft-start interval. cycling the bias input voltage (+12v off then on) resets the counter and the fault latch. gate drive overlap protection the overlap protection circuit ensures that the bo t - tom mosfet does not turn on until the upper mosfet source has reached a voltage low enough to ensure that shoot-through will not o c cur. over-voltage protection during operation, a short on the upper pwm1 mosfet (q1) causes vout1 to increase. when the output exceed the over-voltage threshold of 116% of dacout, the fault pin is set to fault latch and turns q2 on as required in order to reg u - late vout1 to 11 6 % of dacout. the fault latch raises the fault/rt pin close to vcc p o tential. a separate over-voltage circuit provides protection during the initial application of power. for voltage on vcc pin below the power-on reset (and above ~4v), should vsen1 exceed 1. 0 v, the lower mosfet (q2) is driven on as needed to regulate vout1 to 1. 0 v.
aic157 3 14 over-current protection all outputs are protected against excessive over- current. both pwm controller uses upper mosfet?s on-resistance, r ds( on) to monitor the current for protection against shorted outputs. all linear controllers monitor vsen for under-voltage to protect against exce s sive current. when the voltage across q1 (id ?e r ds(on) ) exceeds the level (200 m a ?e r ocset ), this signal inhibit all outputs. discharge soft-start capacitor (c ss ) with 28 m a current sink, and increments the counter. css recharges and initiates a soft-start cycle again until the counter increments to 3. this sets the fault latch to disable all outputs. fig. 6 illustrates the over-current protection until an over load on out1. should excessive current cause vsen to fall below the linear under-voltage threshold, the luv signal sets the over-current latch if css is fully charged. cycling the bias input power (off then on reset the counter and the fault latch. the over-current function for pwm controller will trip at a peak inductor current (i peak ) determined by: i i r r peak ocset ocset ds(on) = the oc trip point varies with mosfet?s temper a - ture. to avoid over-current tripping in the normal o p - erating load range, determine the r ocset resistor from the equation above with: 1. the maximum r ds( on) at the highest jun c tion. 2. the minimum i ocset from the specification t a ble. 3. determine i peak > i out( max) + (inductor ripple cu r rent) /2. out1 voltage program the output voltage of the pwm1 converter is pr o - grammed to discrete levels between 1.3v to 3.5v. the vid pins program an internal voltage reference (dacout) through a ttl compatible 5 bit digital to analog converter. the vid pins can be left open for a logic 1 input, because they are internally pulled up to 5v by a 70k w resistor. changing the vid i n - puts during operation is not recommended. ?11111? vid pin combinations disable the ic and open the pgood pin. out2 voltage selection the agp regulator output voltage is internally set to one of two discrete levels, based on the select pin status. left select pin open, internal pulled high , the output voltage is 3.3v. grounding s e - lect pin will get the 1.5v output vol t age. the status of the select pin can not be changed during operation of the ic without immediatelly causing a fault cond i tion. shutdown neither pwm output switches until the soft-start voltage exceeds the oscillator?s vally voltage. add i - tional, the reference on each linear?s amplifier is clamped to the soft-start voltage. holding the ss pin low turns of all four regul a tors. the vid codes resulting in an inhibit as shown in table 1 also shut down the ic. oscillator synchronization the AIC1573 avoids the problem of cross talk b e - tween the converters by way of phase control method. therefore, for both output voltage settings less than 2.4v or both greater than 2.4v, pwm1 operates out of phase with pwm2. for one pwm output voltage setting below 2.4v and the other pwm output voltage setting of 2.4v and above, pwm1 operates in phase with pwm2.
aic157 3 15 ugate1 ugate2 @v out2 =3.3v @v out1 =1.7v fig. 18 pwm1 operates in phase with pwm2 ugate1 ugate2 @v out1 =1.7v @v out2 =1.5v fig. 19 pwm1 operates out of phase with pwm2 table 1 vout1 voltage program ( 0=connected to gnd, 1=open or connected to 5v ) for all package version pin name pin name vid4 vid3 vid2 vid1 vid0 dacout voltage vid4 vid3 vid2 vid1 vid0 dacout voltage 0 1 1 1 1 1.30v 1 1 1 1 1 inhibit 0 1 1 1 0 1.35v 1 1 1 1 0 2.1 v 0 1 1 0 1 1.40v 1 1 1 0 1 2.2 v 0 1 1 0 0 1.45v 1 1 1 0 0 2.3 v 0 1 0 1 1 1.50v 1 1 0 1 1 2.4 v 0 1 0 1 0 1.55v 1 1 0 1 0 2.5 v 0 1 0 0 1 1.60v 1 1 0 0 1 2.6 v 0 1 0 0 0 1.65v 1 1 0 0 0 2.7 v 0 0 1 1 1 1.70v 1 0 1 1 1 2.8 v 0 0 1 1 0 1.75v 1 0 1 1 0 2.9 v 0 0 1 0 1 1.80 v 1 0 1 0 1 3.0 v 0 0 1 0 0 1.85 v 1 0 1 0 0 3.1 v 0 0 0 1 1 1.90 v 1 0 0 1 1 3.2 v 0 0 0 1 0 1.95 v 1 0 0 1 0 3.3 v 0 0 0 0 1 2.00 v 1 0 0 0 1 3.4 v 0 0 0 0 0 2.05 v 1 0 0 0 0 3.5 v
aic157 3 16 layout considerations any inductance in the switched current path gene r - ates a large voltage spike during the switching i n - terval. the voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device over-voltage stress. careful component selection and tight layout of critical components, and short, wide metal trace minimize the voltage spike. a ground plane should be used. locate the input capacitors (c in ) close to the power switches. minimize the loop formed by c in , the upper mosfet (q1) and the lower mosfet (q2) as possible. connections should be as wide as short as possible to minimize loop i n ductance. the connection between q1, q2 and output indu c - tor should be as wide as short as practical. since this connection has fast voltage transitions will e a - sily i n duce emi. the output capacitor (c out ) should be located as close the load as possible. because minimize the transient load magnitude for high slew rate requires low inductance and resistance in circuit board the AIC1573 is best placed over a quiet ground plane area. the gnd pin should be connected to the groundside of the output capacitors. under no circumstances should gnd be returned to a ground inside the c in , q1, q2 loop. the gnd and pgnd pins should be shorted right at the ic. this help to minimize internal ground disturbances in the ic and prevents differences in ground potential from di s - rupting internal circuit operation. the wiring traces from the control ic to the mo s - fet gate and source should be sized to carry 1a current. the traces for out2 need only be sized for 0.5a. locate cout2 close to the AIC1573. the vcc pin should be decoupled directly to gnd by a 2.2 m f ceramic capacitor, trace lengths should be as short as possible. a multi-layer-printed circuit board is recommended. figure 11 shows the connections of the critical components in the converter. the c in and c out could each represent numerous physical capacitors. dedicate one solid layer for a ground plane and make all critical component ground connections with vias to this layer. pwm output capacitors the load transient for the microprocessor core r e - quires high quality capacitors to supply the high slew rate (di/dt) cu r rent demand. the esr (equivalent series resistance) and esl (equivalent series inductance) parameters rather than actual capacitance determine the buck c a - pacitor values. for a given transient load magnitude, the output voltage transient change due to the ou t - put capacitor can be note by the following equ a tion: d d d d v esr i esl i t out out out = + , where d i out is transient load current step. after the initial transient, the esl dependent term drops off. because the strong relationship between output capacitor esr and output load transient, the output capacitor is usually chosen for esr, not for capacitance value. a capacitor with suitable esr will usually have a larger capacitance value than is needed for energy storage. a common way to lower esr and raise ripple cu r - rent capability is to parallel several capacitors. in most case, multiple electrolytic capacitors of small case size are better than a single large case c a - pacitor.
aic157 3 17 output inductor selection inductor value and type should be chosen based on output slew rate requirement, output ripple requir e - ment and expected peak current. inductor value is primarily controlled by the required current respo n - se time. the AIC1573 will provide either 0% or 100% duty cycle in response to a load transient. the response time to a transient is different for the application of load and remove of load. t l i v v rise out in out = - d , t = l i v fall out out d . where d i out is transient load current step . in a typical 5v input, 2v output application, a 3 m h inductor has a 1a/ m s rise time, resulting in a 5 m s delay in responding to a 5a load current step. to optimize performance, different combinations of i n - put and output voltage and expected loads may r e - quire different inductor value. a smaller value of i n - ductor will improve the transient response at the expense of increase output ripple voltage and i n - ductor core saturation rating. peak current in the inductor will be equal to the maximum output load current plus half of inductor ripple current. the ripple current is approximately equal to: i = (v v ) v l v ripple in out out in - f ; f = AIC1573 oscillator frequency. the inductor must be able to withstand peak cu r - rent without saturation, and the copper resistance in the winding should be kept as low as possible to min i mize resistive power loss input capacitor selection most of the input supply current is supplied by the input bypass capacitor , the resulting rms current flow in the input capacitor will heat it up. use a mix of input bulk capacitors to control the voltage ove r - shoot across the upper mosfet. the ceramic c a - pacitance for the high frequency decoupling should be placed very close to the upper mosfet to su p - press the voltage induced in the parasitic circuit impedance. the buck capacitors to supply the rms current is a p proximate equal to: i (1 d) d i 1 12 v d f l rms 2 out in 2 = - + ? ? ? ? , where d v v out in = the capacitor voltage rating should be at least 1.25 times greater than the maximum input vol t age. pwm mosfet selection in high current pwm application, the mosfet power dissipation, package type and heatsink are the dominant design factors. the conduction loss is the only component of power dissipation for the lower mosfet, since it turns on into near zero voltage. the upper mosfet has conduction loss and switching loss. the gate charge losses are proportional to the switching frequency and are di s - sipated by the AIC1573. however, the gate charge increases the switching interval, t sw , which increase the upper mosfet switching losses. ensure that both mosfets are within their maximum junction temperature at high ambient temperature by calc u - lating the temperature rise according to package thermal resistance specific a tions. p i r d i v t f 2 upper out 2 ds(on) out in sw = + p i r d) lower out 2 ds(on) = - ( 1 the equations above do not model power loss due to the reverse recovery of the lower mosfet?s b o - dy diode. the r ds( on) is different for the two previous equ a - tions even if the type devices is used for both. this
aic157 3 18 is because the gate drive applied to the upper mosfet is different than the lower mosfet. logic level mosfets should be selected based on on-resistance considerations, r ds( on) should be chosen base on input and output voltage, allowable power dissipation and maximum required output current. power dissipation should be calculated based primarily on required efficiency or allowable thermal dissipation. rectifier schottky diode is a clamp that prevent the loss parasitic mosfet body diode from conducting during the dead time between the turn off of the lower mosfet and the turn on of the upper mosfet. the diode?s rated reverse breakdown voltage must be greater than twice the maximum input voltage. linear controller mosfet selection the power dissipated in a linear regulator is: ) v (v i p out in out linear - = select a package and heatsink that maintains jun c - tion temperature below the maximum rating while operation at the highest expected ambient temper a - ture. linear output capacitor the output capacitors for the linear regulator and linear controller provide dynamic load current. the linear controller uses dominant pole compensation integrated in the error amplifier and is insensitive to output capacitor selection. cout3 and cout4 should be selected for transient load regulation. the output capacitor for the linear regulator provides loop st a bility. pwm feedback analysis + vdac v out vea pwm comp. networks compensation error amp. r esr l o d v osc c o q2 q1 v in modulation gain fig 20. control loop the compensation network consists of the error amplifier and built in compensation networks. the goal of the compensation network is to provide for fast response and adequate phase margin. phase margin is the difference between the closed loop phase at 0db and 180 degree. closed loop gain(db) = modulation gain(db) + compensation gain (db) modulation gain(db) ? ? ? ? ? ? ? ? ? ? ? + + ? ? ? ? ? d ? 2 1 log 10 log 20 esr osc in f f v v
aic157 3 19 ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? - - 2 2 2 1 log 10 q f f f f lc lc where o o lc c l f p 2 1 = ; o esr esr c r f = p 2 1 ; load o o esr o o r c l r l c q 1 1 + = the break frequency of internal compensation gain are given by khz f z 6 . 2 1 = ; khz f z 24 2 = ; khz f p 30 1 = ; khz f p 400 2 = 100 1k 10k 100k 1m 10m -20 0 20 40 60 f frequency ( khz) f odb 20log(v in / d v osc ) f esr f lc f z1 f z2 f p2 f p1 modulation gain compensation gain closed loop gain gain (d b ) fig. 21 bode plot of converter gain bode plot of converter gain sampling theory shows that f 0db must be less that half the switching frequency for the loop stables . but it must be considerably less than that, or there will be large amplitude switching frequency ripple at the output. thus, the usual practices is to fix f 0db at 1/4 to 1/5 the switc h ing frequency. n physical dimensions l 2 8 lead plastic so (unit: mm) symbol min max a 2.35 2.65 a1 0.10 0.30 b 0.33 0.51 c 0.23 0.32 d 17.70 18.10 e 7.40 7.60 e 1.27 (typ) h 10.00 10.65 l 0.40 1.27 d c l e h e b a a1

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